Parhi received the B. Tech. degree from the Indian Institute of Technology,Kharagpur in 1982,the M.S. degree from the University of Pennsylvania in 1984,and the Ph.D. degree from the University of California,Berkeley in 1988. He joined the Department of Electrical and Computer Engineering at the University of Minnesota,Twin Cities in October 1988. He was promoted to Associate Professor with tenure in July 1992 and promoted to full professor in July 1995. From July 1997 to June 2022,he held the Edgar F. Johnson Professorship in Electronic Communication. Since July 2022,he holds the Erwin A. Kelen Chair in Electrical Engineering. From July 2008 to August 2011,he served as the Director of Graduate Studies of the Electrical Engineering Program.[1]
His research has led to high-speed architectures for cryptosystems such as the advanced encryption standard (AES),[24]post-quantum cryptography,[25] and homomorphic encryption.[26] He has also developed approaches to obfuscating integrated circuits using keys to prevent the sale of excess parts and to protect key parameters of the design.[27][28] In the 1990s,Parhi worked on a DARPA funded project on high-level synthesis that led to the development of the Minnesota Architecture Synthesis System (MARS) for time-constrained and resource-constrained synthesis of data-flow graphs.[29] His research group also developed the Hierarchical Energy Analysis Tool (HEAT) to estimate power consumption with circuit-simulation-level accuracy from logic-level simulation.[30]
Literary works
Keshab K. Parhi (1999). VLSI Digital Signal Processing Systems: Design and Implementation. Wiley-Interscience. ISBN978-0-471-24186-7.
Shanbhag, N.R.; Keshab K. Parhi (1994). Pipelined Adaptive Digital Filters (The Springer International Series in Engineering and Computer Science, 274). Springer. ISBN978-1-4613-6151-0.
Hartley, R.; Keshab K. Parhi (1995). Digit-Serial Computation (The Springer International Series in Engineering and Computer Science, 316). Springer. ISBN978-1-4613-5985-2.
Chung, J.-G.; Keshab K. Parhi (1996). Pipelined Lattice and Wave Digital Recursive Filters. The Springer International Series in Engineering and Computer Science. Vol.344. Springer. ISBN978-1-4612-8560-1.
Keshab K. Parhi; Nishitani, T. (1999). Digital Signal Processing for Multimedia Systems (Signal Processing and Communications). CRC Press. ISBN9780824719241.
Parhi has also authored over 725 papers and is inventor or co-inventor of 36 issued US patents.[31]
2017 – IEEE Circuits and Systems SocietyMac Van Valkenburg Award for pioneering contributions to VLSI digital signal processing architectures, design methodologies, and their applications to wired and wireless communications, and service to IEEE Circuits and Systems Society[38]
2012 – IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award for contributions to VLSI architectures and design methodologies for digital signal processing and communications circuits and systems.[41]
2003 – IEEE Kiyo Tomiyasu Award for pioneering contributions to high-speed and low-power digital signal processing architectures for broadband communications systems[43]
↑ Parhi, K.K. (December 1989). "Algorithm Transformation Techniques for Concurrent Processors". Proceedings of the IEEE. 77 (12): 1879–1895. doi:10.1109/5.48830.
↑ Parhi, K.K.; Messerschmitt, D.G. (February 1991). "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding". IEEE Transactions on Computers. 40 (2): 178–195. doi:10.1109/12.73588.
↑ Parhi, K.K.; Wang, C.-Y.; Brown, A.P. (January 1992). "Synthesis of Control Circuits in Folded Pipelined DSP Architectures". IEEE Journal of Solid-State Circuits. 27 (1): 29–43. Bibcode:1992IJSSC..27...29P. doi:10.1109/4.109555.
↑ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in Recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1099–1117. doi:10.1109/29.32286.
↑ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1118–1134. doi:10.1109/29.32287.
↑ Shanbhag, N.R.; Parhi, K.K. (December 1993). "Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 40 (12): 753–766. doi:10.1109/82.260240.
↑ Parhi, K.K. (July 1991). "Pipelining in Algorithms with Quantizer Loops". IEEE Transactions on Circuits and Systems. 38 (7): 745–754. doi:10.1109/31.135746.
↑ Parhi, K.K. (April 2005). "Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13 (4): 489–493. doi:10.1109/TVLSI.2004.842935.
↑ Gu, Y.; Parhi, K.K. (September 2007). "High-Speed Architecture Design of Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems I: Regular Papers. 54 (9): 1929–1937. Bibcode:2007ITCSR..54.1929G. doi:10.1109/TCSI.2007.904688.
↑ Gu, Y.; Parhi, K.K. (May 2008). "Design of Parallel Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems II: Express Briefs. 55 (5): 447–451. Bibcode:2008ITCSE..55..447G. doi:10.1109/TCSII.2007.914435.
↑ Gu, Y.; Parhi, K.K. (February 2007). "Pipelined Parallel Decision Feedback Decoders for High-Speed Ethernet over Copper". IEEE Transactions on Signal Processing. 55 (2): 707–715. Bibcode:2007ITSP...55..707G. doi:10.1109/TSP.2006.885776.
↑ Cheng, C.; Parhi, K.K. (October 2007). "High-Throughput VLSI Architecture for FFT Computation". IEEE Transactions on Circuits and Systems II: Express Briefs. 54 (10): 863–867. Bibcode:2007ITCSE..54..863C. doi:10.1109/TCSII.2007.901635.
↑ Ayinala, M.; Brown, M.J.; Parhi, K.K. (June 2012). "Pipelined Parallel FFT Architectures via Folding Transformation". IEEE Transactions on VLSI Systems. 20 (6): 1068–1081. Bibcode:2012ITVL...20.1068A. doi:10.1109/TVLSI.2011.2147338.
↑ Parhi, K.K. (April 2024). A Low-Latency FFT-IFFT Cascade Architecture. Proc. of 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). pp.181–185. arXiv:2309.09035. doi:10.1109/ICASSP48485.2024.10447370.
↑ Wang, Z.; Chi, Z.; Parhi, K.K. (December 2002). "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders". IEEE Transactions on VLSI Systems. 10 (12): 902–912. doi:10.1109/TVLSI.2002.808451.
↑ Chen, Y.; Parhi, K.K. (June 2004). "Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes". IEEE Transactions on Circuits and Systems I: Regular Papers. 51 (6): 1106–1113. doi:10.1109/TCSI.2004.826194.
↑ Yuan, B.; Parhi, K.K. (April 2014). "Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding". IEEE Transactions on Circuits and Systems I: Regular Papers. 61 (4): 1241–1254. Bibcode:2014ITCSR..61.1241Y. doi:10.1109/TCSI.2013.2283779.
↑ Yuan, B.; Parhi, K.K. (December 15, 2014). "Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders". IEEE Transactions on Signal Processing. 62 (24): 6496–6506. Bibcode:2014ITSP...62.6496Y. doi:10.1109/TSP.2014.2366712.
↑ Zhang, X.; Parhi, K.K. (September 2004). "High-Speed VLSI Architectures for the AES Algorithm". IEEE Transactions on VLSI Systems. 12 (9): 957–967. doi:10.1109/TVLSI.2004.832943.
↑ Tan, W.; Wang, A.; Zhang, X.; Lao, Y.; Parhi, K.K. (September 2023). "High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography". IEEE Transactions on Computers. 72 (9): 2454–2466. arXiv:2110.12127. Bibcode:2023ITCmp..72.2454T. doi:10.1109/TC.2023.3251847.
↑ Tan, W.; Chiu, S.-W.; Wang, A.; Lao, Y.; Parhi, K.K. (January 2024). "PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption". IEEE Transactions on Information Forensics and Security. 19: 1646–1659. arXiv:2303.02237. Bibcode:2024ITIF...19.1646T. doi:10.1109/TIFS.2023.3338553.
This page is based on this Wikipedia article Text is available under the CC BY-SA 4.0 license; additional terms may apply. Images, videos and audio are available under their respective licenses.
