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Cascode voltage switch logic

Last updated December 28, 2025

Implementation of CVSL with a general Pull Down Network, where PDN1 and PDN2 must be mutually exclusive DCVSL.svg — Implementation of CVSL with a general Pull Down Network, where PDN1 and PDN2 must be mutually exclusive

Cascode Voltage Switch Logic (CVSL) refers to a CMOS-type logic family which is designed for certain advantages. It requires mainly N-channel MOSFET transistors to implement the logic using true and complementary input signals, and also needs two P-channel transistors at the top to pull one of the outputs high. This logic family is also known as Differential Cascode Voltage Switch Logic (DCVS or DCVSL).

References

Weste and Harris, CMOS VLSI Design, Third Edition ( ISBN 0-321-14901-7; ISBN 0-321-26977-2 (international edition))

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v t e Logic families
MOS technology	PMOS logic NMOS logic Depletion-load NMOS logic (including HMOS) Complementary MOS (CMOS) Pass transistor logic (PTL) Bipolar–CMOS (BiCMOS)
Other technologies	Diode logic Diode–transistor logic (DTL) Open collector (OC) Direct-coupled transistor logic (DCTL) Emitter-coupled logic (ECL) Gunning transceiver logic (GTL) Integrated injection logic (I²L) Resistor–transistor logic (RTL) Transistor–transistor logic (TTL) Current-mode logic / source-coupled logic (CML/SCL)
Types	Static Dynamic Domino logic Four-phase logic

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Cascode voltage switch logic

See also

References